Invention Application
US20120313146A1 TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
审中-公开
晶体管和形成晶体管的方法具有降低的基极电阻
- Patent Title: TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE
- Patent Title (中): 晶体管和形成晶体管的方法具有降低的基极电阻
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Application No.: US13155730Application Date: 2011-06-08
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Publication No.: US20120313146A1Publication Date: 2012-12-13
- Inventor: Marc W. Cantell , Thai Doan , Jessica A. Levy , Qizhi Liu , William J. Murphy , Christa R. Willets
- Applicant: Marc W. Cantell , Thai Doan , Jessica A. Levy , Qizhi Liu , William J. Murphy , Christa R. Willets
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L29/737
- IPC: H01L29/737 ; H01L21/331 ; H01L29/73

Abstract:
Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
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