Invention Application
US20120317531A1 METHOD AND APPARATUS FOR PERFORMING VIA ARRAY MERGING AND PARASITIC EXTRACTION 有权
用于通过阵列合并和PARASITIC提取来执行的方法和装置

  • Patent Title: METHOD AND APPARATUS FOR PERFORMING VIA ARRAY MERGING AND PARASITIC EXTRACTION
  • Patent Title (中): 用于通过阵列合并和PARASITIC提取来执行的方法和装置
  • Application No.: US13362583
    Application Date: 2012-01-31
  • Publication No.: US20120317531A1
    Publication Date: 2012-12-13
  • Inventor: Krishnakumar Sundaresan
  • Applicant: Krishnakumar Sundaresan
  • Applicant Address: US CA Mountain View
  • Assignee: SYNOPSYS, INC.
  • Current Assignee: SYNOPSYS, INC.
  • Current Assignee Address: US CA Mountain View
  • Main IPC: G06F17/50
  • IPC: G06F17/50
METHOD AND APPARATUS FOR PERFORMING VIA ARRAY MERGING AND PARASITIC EXTRACTION
Abstract:
Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M≧2, N≧2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via.
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