发明申请
US20120319270A1 Wafer Level Chip Scale Package with Reduced Stress on Solder Balls
有权
晶圆级芯片级封装,减少了焊球的应力
- 专利标题: Wafer Level Chip Scale Package with Reduced Stress on Solder Balls
- 专利标题(中): 晶圆级芯片级封装,减少了焊球的应力
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申请号: US13162394申请日: 2011-06-16
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公开(公告)号: US20120319270A1公开(公告)日: 2012-12-20
- 发明人: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
- 申请人: Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 主分类号: H01L23/48
- IPC分类号: H01L23/48
摘要:
A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.
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