A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.