Methods and apparatus relating to an image signal processor architecture that may be optimized for low-power consumption, processing flexibility, and/or user experience are described. In an embodiment, an image signal processor may be partitioned into a plurality of partitions. Each partition may be capable of entering a lower power consumption state. Also, processing by each partition may be done in various modes to optimize for low-power consumption, processing flexibility, and/or user experience. Other embodiments are also disclosed and claimed.