An image processing circuit and an image processing method are disclosed. The image processing circuit comprises a block matching unit, a multiplexer, an arbiter, and a motion compensation circuit. The block matching unit calculates an alternating current (AC) sum of absolute difference (SAD) and a direct current (DC) sum of absolute difference (SAD) according to a current block in a current image and a reference block in a reference image. The arbiter controls the multiplexer selectively to output the AC SAD or the DC SAD according to an arbitration rule related to a scene characteristic of the current image. The motion compensation circuit executes motion compensation according to the AC SAD or the DC SAD outputted by the multiplexer.