One aspect of the present invention is a three-dimensional integrated circuit 1 including a first semiconductor chip and a second semiconductor chip that are layered on each other, wherein each of (i) a wiring layer closest to an interface between the first and second semiconductor chips among wiring layers of the first semiconductor chip and (ii) a wiring layer closest to the interface among wiring layers of the second semiconductor chip includes a power conductor area and a ground conductor area, a layout of the power conductor area and the ground conductor area in the first semiconductor chip is the same as a layout of the power conductor area and the ground conductor area in the second semiconductor chip, and the power conductor area in the first semiconductor chip at least partially faces the ground conductor area in the second semiconductor chip with an insulation layer therebetween.