Invention Application
US20130043600A1 BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE 有权
结合的半导体结构,包括两个或更多加工的半导体结构,由普通基底

  • Patent Title: BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE
  • Patent Title (中): 结合的半导体结构,包括两个或更多加工的半导体结构,由普通基底
  • Application No.: US13657327
    Application Date: 2012-10-22
  • Publication No.: US20130043600A1
    Publication Date: 2013-02-21
  • Inventor: Mariam Sadaka
  • Applicant: SoitecMariam Sadaka
  • Applicant Address: FR Crolles Cedex US TX Austin
  • Assignee: SOITEC,Mariam Sadaka
  • Current Assignee: SOITEC,Mariam Sadaka
  • Current Assignee Address: FR Crolles Cedex US TX Austin
  • Main IPC: H01L23/522
  • IPC: H01L23/522
BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE
Abstract:
Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.
Information query
Patent Agency Ranking
0/0