发明申请
US20130046934A1 SYSTEM CACHING USING HETEROGENOUS MEMORIES 审中-公开
使用异构记忆的系统缓存

SYSTEM CACHING USING HETEROGENOUS MEMORIES
摘要:
A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.
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