发明申请
- 专利标题： COMPUTING VALIDATION COVERAGE OF INTEGRATED CIRCUIT MODEL
- 专利标题（中）： 集成电路模型的计算验证覆盖
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申请号： US13444094申请日： 2012-04-11
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公开(公告)号： US20130055179A1公开(公告)日： 2013-02-28
- 发明人: Bo Fan , Liang Chen , Yongfeng Pan , Fan S.H. Zhou
- 申请人： Bo Fan , Liang Chen , Yongfeng Pan , Fan S.H. Zhou
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 优先权： CN201110270261.1 20110831
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Embodiments of the present invention provide a method of computing validation coverage of an integrated circuit model, comprising: obtaining a logical structure of a integrated circuit model under validation; searching and recording signal paths in the integrated circuit model under validation based on the logical structure; and computing coverage of validation with respect to the signal paths. According to the technical solution as provided in the embodiments of the present invention, a signal path-based validation coverage may be obtained, thereby providing data regarding validation completeness more accurately.
公开/授权文献
- US08495536B2 Computing validation coverage of integrated circuit model 公开/授权日：2013-07-23
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