发明申请
US20130061111A1 SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST
有权
同时进行数据传输和错误控制以减少延迟并将其改善到主机
- 专利标题： SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST
- 专利标题（中）： 同时进行数据传输和错误控制以减少延迟并将其改善到主机
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申请号： US13224714申请日： 2011-09-02
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公开(公告)号： US20130061111A1公开(公告)日： 2013-03-07
- 发明人: Christopher J. Sarcone , David G. Conroy , Jim Keller
- 申请人： Christopher J. Sarcone , David G. Conroy , Jim Keller
- 申请人地址： US CA Cupertino
- 专利权人： APPLE INC.
- 当前专利权人： APPLE INC.
- 当前专利权人地址： US CA Cupertino
- 主分类号： H03M13/29
- IPC分类号： H03M13/29 ; G06F11/10
摘要：
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.
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