发明申请
US20130065367A1 Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers
审中-公开
使用减少的间隔物形成高度缩放的半导体器件的方法
- 专利标题： Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers
- 专利标题（中）： 使用减少的间隔物形成高度缩放的半导体器件的方法
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申请号： US13231470申请日： 2011-09-13
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公开(公告)号： US20130065367A1公开(公告)日： 2013-03-14
- 发明人: Stefan Flachowsky , Thilo Scheiper , Ricardo P. Mikalo
- 申请人： Stefan Flachowsky , Thilo Scheiper , Ricardo P. Mikalo
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人地址： KY Grand Cayman
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.
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