- 专利标题: IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
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申请号: US13471623申请日: 2012-05-15
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公开(公告)号: US20130067425A1公开(公告)日: 2013-03-14
- 发明人: Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
- 申请人: Douglas W. Kemerer , Edward W. Seibert , Lijiang L. Wang
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.