- 专利标题: VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE
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申请号: US13611113申请日: 2012-09-12
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公开(公告)号: US20130095623A1公开(公告)日: 2013-04-18
- 发明人: Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
- 申请人: Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.
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