发明申请
- 专利标题: FREQUENCY DIVIDER AND PLL CIRCUIT
- 专利标题(中): 频率分路器和PLL电路
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申请号: US13671938申请日: 2012-11-08
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公开(公告)号: US20130120073A1公开(公告)日: 2013-05-16
- 发明人: Kenichi OKADA , Ahmed Magdi Hassan MUSA
- 申请人: Semiconductor Technology Academic Research C
- 申请人地址: JP Yokohama-shi
- 专利权人: Semiconductor Technology Academic Research Center
- 当前专利权人: Semiconductor Technology Academic Research Center
- 当前专利权人地址: JP Yokohama-shi
- 优先权: JP2011-246362 20111110
- 主分类号: H03L5/00
- IPC分类号: H03L5/00
摘要:
A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.
公开/授权文献
- US08860511B2 Frequency divider and PLL circuit 公开/授权日:2014-10-14
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