发明申请
- 专利标题： STRAINED TRANSISTOR INTEGRATION FOR CMOS
- 专利标题（中）： CMOS的应变晶体管集成
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申请号： US13764675申请日： 2013-02-11
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公开(公告)号： US20130153965A1公开(公告)日： 2013-06-20
- 发明人: Boyan Boyanov , Anand Murthy , Brian S. Doyle , Robert Chau
- 申请人： Boyan Boyanov , Anand Murthy , Brian S. Doyle , Robert Chau
- 主分类号： H01L29/78
- IPC分类号： H01L29/78
摘要：
Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
公开/授权文献
- US08748869B2 Strained transistor integration for CMOS 公开/授权日：2014-06-10
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