发明申请
- 专利标题： Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties
- 专利标题（中）： 半导体器件和与具有扩展的互连表面积的导电垫形成互连结构的方法，用于增强的互连特性
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申请号： US13768862申请日： 2013-02-15
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公开(公告)号： US20130154090A1公开(公告)日： 2013-06-20
- 发明人: DaeSik Choi , OhHan Kim , SungWon Cho
- 申请人： STATS ChipPAC, Ltd.
- 申请人地址： SG Singapore
- 专利权人： STATS CHIPPAC, LTD.
- 当前专利权人： STATS CHIPPAC, LTD.
- 当前专利权人地址： SG Singapore
- 主分类号： H01L21/56
- IPC分类号： H01L21/56 ; H01L23/498
摘要：
A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
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