发明申请
- 专利标题： INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COUPLING FEATURES AND METHOD OF MANUFACTURE THEREOF
- 专利标题（中）： 具有耦合特性的集成电路包装系统及其制造方法
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申请号： US13326116申请日： 2011-12-14
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公开(公告)号： US20130154107A1公开(公告)日： 2013-06-20
- 发明人: MinJung Kim , DaeSik Choi , WonIl Kwon
- 申请人： MinJung Kim , DaeSik Choi , WonIl Kwon
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/768
摘要：
A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.
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