发明申请
- 专利标题: VALIDATING INTERCONNECTIONS BETWEEN LOGIC BLOCKS IN A CIRCUIT DESCRIPTION
- 专利标题(中): 验证电路中逻辑块之间的互连
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申请号: US13365370申请日: 2012-02-03
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公开(公告)号: US20130205268A1公开(公告)日: 2013-08-08
- 发明人: Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
- 申请人: Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague , Michael A. Ziegerhofer
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
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