发明申请
- 专利标题: METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS
- 专利标题(中): 用于分解电路设计层和使用分解图案制作半导体器件的方法
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申请号: US13400445申请日: 2012-02-20
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公开(公告)号: US20130219347A1公开(公告)日: 2013-08-22
- 发明人: Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
- 申请人: Yi Zou , Swamy Muddu , Lynn T. Wang , Vito Dai , Luigi Capodieci , Peng Xie
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.
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