发明申请
- 专利标题: METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION
- 专利标题(中): 用减少电气参数变化制造集成电路的方法
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申请号: US13421604申请日: 2012-03-15
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公开(公告)号: US20130244388A1公开(公告)日: 2013-09-19
- 发明人: Thilo Scheiper , Stefan Flachowsky , Shesh Mani Pandey
- 申请人: Thilo Scheiper , Stefan Flachowsky , Shesh Mani Pandey
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.
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