发明申请
- 专利标题: APPARATUS AND METHOD FOR INTEGRATION OF THROUGH SUBSTRATE VIAS
- 专利标题(中): 通过基板VIAS整合的装置和方法
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申请号: US13445636申请日: 2012-04-12
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公开(公告)号: US20130270711A1公开(公告)日: 2013-10-17
- 发明人: Jeremiah HEBDING , Megha RAO , Colin McDONOUGH , Matthew SMALLEY , Douglas Duane COOLBAUGH , Joseph PICCIRILLO, JR. , Stephen G. BENNETT , Michael LIEHR , Daniel PASCUAL
- 申请人: Jeremiah HEBDING , Megha RAO , Colin McDONOUGH , Matthew SMALLEY , Douglas Duane COOLBAUGH , Joseph PICCIRILLO, JR. , Stephen G. BENNETT , Michael LIEHR , Daniel PASCUAL
- 申请人地址: US NY Albany
- 专利权人: The Research Foundation Of State University Of New York
- 当前专利权人: The Research Foundation Of State University Of New York
- 当前专利权人地址: US NY Albany
- 主分类号: H01L23/538
- IPC分类号: H01L23/538 ; H01L21/762 ; H01L21/50 ; H01L21/768
摘要:
An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.
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