A particular method of making a stacked multi-die semiconductor device includes forming a stack of at least two dies. Each die includes a chip identifier structure that includes a first set of at least two through vias that are each hard wired to a set of external electrical contacts. Each die further includes chip identifier selection logic coupled to the chip identifier structure. Each die further includes a chip select structure that includes a second set of at least two through vias coupled to the chip identifier selection logic. The method further includes coupling each external electrical contact to a voltage source or ground. Each of the first set of through vias has a pad that is coupled to an adjacent through via and each of the second set of through vias is coupled to its own respective pad.