发明申请
US20130302956A1 Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers
有权
用嵌入式半导体材料形成半导体器件作为源/漏区域的方法使用减少的间隔数
- 专利标题： Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers
- 专利标题（中）： 用嵌入式半导体材料形成半导体器件作为源/漏区域的方法使用减少的间隔数
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申请号： US13470454申请日： 2012-05-14
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公开(公告)号： US20130302956A1公开(公告)日： 2013-11-14
- 发明人: Stefan Flachowsky , Ricardo P. Mikalo , Jan Hoentschel
- 申请人： Stefan Flachowsky , Ricardo P. Mikalo , Jan Hoentschel
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人地址： KY Grand Cayman
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.
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