发明申请
- 专利标题： CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY
- 专利标题（中）： CHUNK REDUNDANCY建筑记忆
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申请号： US13995169申请日： 2012-03-29
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公开(公告)号： US20130332674A1公开(公告)日： 2013-12-12
- 发明人: Toru Tanzawa
- 申请人： Toru Tanzawa
- 国际申请： PCT/US2012/031247 WO 20120329
- 主分类号： G06F11/10
- IPC分类号： G06F11/10 ; G06F3/06
摘要：
An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.
公开/授权文献
- US09727417B2 Chunk redundancy architecture for memory 公开/授权日：2017-08-08
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