Invention Application
- Patent Title: ELECTRICAL INTERCONNECTION STRUCTURES INCLUDING STRESS BUFFER LAYERS
- Patent Title (中): 电气互连结构包括应力缓冲层
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Application No.: US13797655Application Date: 2013-03-12
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Publication No.: US20130334656A1Publication Date: 2013-12-19
- Inventor: Jeonggi JIN , Jeong-woo PARK , Ju-il Choi
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2012-0063075 20120613
- Main IPC: H01L23/525
- IPC: H01L23/525
Abstract:
Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.
Public/Granted literature
- US08872306B2 Electrical interconnection structures including stress buffer layers Public/Granted day:2014-10-28
Information query
IPC分类:
