发明申请
US20140001441A1 INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
有权
用于制造纳米器件的内部间隔件的集成方法
- 专利标题： INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- 专利标题（中）： 用于制造纳米器件的内部间隔件的集成方法
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申请号： US13539195申请日： 2012-06-29
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公开(公告)号： US20140001441A1公开(公告)日： 2014-01-02
- 发明人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Mark Armstrong , Rafael Rios , Abhijit Jayant Pethe , Willy Rachmady
- 申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Mark Armstrong , Rafael Rios , Abhijit Jayant Pethe , Willy Rachmady
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/336 ; B82Y40/00 ; B82Y99/00
摘要：
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
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