An integrated circuit 114 includes processing pipeline circuitry 40 comprising a plurality of pipeline stages 44, 46, 48 separated by respective signal value storage circuitry 48, 50, 52. Timing detection circuitry 54, 56, 58 coupled to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry 66 triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal CK controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.