Invention Application
- Patent Title: DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS
- Patent Title (中): 超级电子产品加工制造双重屏蔽技术
-
Application No.: US13771330Application Date: 2013-02-20
-
Publication No.: US20140054552A1Publication Date: 2014-02-27
- Inventor: Sergey K. Tolpygo
- Applicant: Hypres, Inc.
- Applicant Address: US NY Elmsford
- Assignee: HYPRES, INC.
- Current Assignee: HYPRES, INC.
- Current Assignee Address: US NY Elmsford
- Main IPC: H01L39/02
- IPC: H01L39/02 ; H01L39/24

Abstract:
An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
Public/Granted literature
- US09136457B2 Double-masking technique for increasing fabrication yield in superconducting electronics Public/Granted day:2015-09-15
Information query
IPC分类: