Invention Application
US20140054552A1 DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS 有权
超级电子产品加工制造双重屏蔽技术

  • Patent Title: DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS
  • Patent Title (中): 超级电子产品加工制造双重屏蔽技术
  • Application No.: US13771330
    Application Date: 2013-02-20
  • Publication No.: US20140054552A1
    Publication Date: 2014-02-27
  • Inventor: Sergey K. Tolpygo
  • Applicant: Hypres, Inc.
  • Applicant Address: US NY Elmsford
  • Assignee: HYPRES, INC.
  • Current Assignee: HYPRES, INC.
  • Current Assignee Address: US NY Elmsford
  • Main IPC: H01L39/02
  • IPC: H01L39/02 H01L39/24
DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS
Abstract:
An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
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