- 专利标题： LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS
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申请号： US13601394申请日： 2012-08-31
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公开(公告)号： US20140061936A1公开(公告)日： 2014-03-06
- 发明人: Victor Moroz , Jamil Kawa
- 申请人： Victor Moroz , Jamil Kawa
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; G06F17/50 ; H01L21/768
摘要：
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
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