发明申请
- 专利标题: METHOD TO ENHANCE DOUBLE PATTERNING ROUTING EFFICIENCY
- 专利标题(中): 增强双重路线路由效率的方法
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申请号: US13603304申请日: 2012-09-04
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公开(公告)号: US20140068543A1公开(公告)日: 2014-03-06
- 发明人: Lei Yuan , Jongwook Kye
- 申请人: Lei Yuan , Jongwook Kye
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人地址: KY Grand Cayman
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method for enabling jogging functionality in circuit designs utilizing DPT without the need for difficult to implement tools such as stitch-aware routing tools is disclosed. Embodiments include: displaying a user interface for generating an IC having a plurality of masks for a single layer; causing, at least in part, a presentation in the user interface of a cell placement of the IC that includes a filler cell; and designating a portion of the filler cell as a routing zone, the routing zone being configured such that routes placed in the routing zone are decomposable with other routes placed outside the filler cell.
公开/授权文献
- US08719757B2 Method to enhance double patterning routing efficiency 公开/授权日:2014-05-06