- 专利标题: HYBRID PHASE-LOCKED LOOP ARCHITECTURES
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申请号: US13608277申请日: 2012-09-10
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公开(公告)号: US20140070855A1公开(公告)日: 2014-03-13
- 发明人: Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
- 申请人: Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: H03L7/107
- IPC分类号: H03L7/107
摘要:
Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.
公开/授权文献
- US08704566B2 Hybrid phase-locked loop architectures 公开/授权日:2014-04-22