A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.