- 专利标题: Power Gating A Portion Of A Cache Memory
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申请号: US13785228申请日: 2013-03-05
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公开(公告)号: US20140173206A1公开(公告)日: 2014-06-19
- 发明人: Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
- 申请人: Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
- 主分类号: G06F12/08
- IPC分类号: G06F12/08
摘要:
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
公开/授权文献
- US09176875B2 Power gating a portion of a cache memory 公开/授权日:2015-11-03