A display device includes pixels respectively arranged in areas defined by gate lines and data lines, a gate driver that drives the gate lines in response to a gate pulse signal, a data driver that drives the data lines in response to a clock signal and a data signal, and a timing controller that applies the clock signal and the data signal to the data driver and the gate pulse signal to the gate driver in response to an image signal and a control signal. The timing controller periodically changes a pulse width of each of the gate pulse signal and the clock signal.