发明申请
US20140177361A1 SEMICONDUCTOR DEVICE INCLUDING A CLOCK GENERATING CIRCUIT FOR GENERATING AN INTERNAL SIGNAL HAVING A COARSE DELAY LINE, A FINE DELAY LINE AND A SELECTOR CIRCUIT
有权
包括用于产生具有粗糙延迟线，精细延迟线和选择器电路的内部信号的时钟发生电路的半导体器件
- 专利标题： SEMICONDUCTOR DEVICE INCLUDING A CLOCK GENERATING CIRCUIT FOR GENERATING AN INTERNAL SIGNAL HAVING A COARSE DELAY LINE, A FINE DELAY LINE AND A SELECTOR CIRCUIT
- 专利标题（中）： 包括用于产生具有粗糙延迟线，精细延迟线和选择器电路的内部信号的时钟发生电路的半导体器件
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申请号： US14193345申请日： 2014-02-28
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公开(公告)号： US20140177361A1公开(公告)日： 2014-06-26
- 发明人: Katsuhiro KITAGAWA
- 申请人： Katsuhiro KITAGAWA
- 优先权： JP2009-062882 20090316
- 主分类号： G11C7/22
- IPC分类号： G11C7/22
摘要：
A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.