A duty cycle detection and correction circuit includes a clock generator, a clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal, and the first clock signal and the second clock signal have a predetermined phase difference. The clock tree is configured to receive the first clock signal and the second clock signal, to generate a first output clock signal based on the first clock signal and the set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.