发明申请
- 专利标题: INSTRUCTION FOR FAST ZUC ALGORITHM PROCESSING
- 专利标题(中): 用于快速ZUC算法处理的指令
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申请号: US13730230申请日: 2012-12-28
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公开(公告)号: US20140189290A1公开(公告)日: 2014-07-03
- 发明人: Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
- 申请人: Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
- 主分类号: G06F15/76
- IPC分类号: G06F15/76
摘要:
Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
公开/授权文献
- US09490971B2 Instruction for fast ZUC algorithm processing 公开/授权日:2016-11-08