Invention Application
- Patent Title: FAULT DETECTION IN INSTRUCTION TRANSLATIONS
- Patent Title (中): 指导翻译中的故障检测
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Application No.: US13728669Application Date: 2012-12-27
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Publication No.: US20140189310A1Publication Date: 2014-07-03
- Inventor: Nathan Tuck , David Dunn , Ross Segelken , Madhu Swarna
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.
Information query