发明申请
US20140189433A1 MEMORY SUBSYSTEM PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
有权
基于内部系统弱位检测的记忆子系统性能
- 专利标题: MEMORY SUBSYSTEM PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
- 专利标题(中): 基于内部系统弱位检测的记忆子系统性能
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申请号: US13730429申请日: 2012-12-28
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公开(公告)号: US20140189433A1公开(公告)日: 2014-07-03
- 发明人: THEODORE Z. SCHOENBORN , CHRISTOPHER P. MOZAK
- 申请人: THEODORE Z. SCHOENBORN , CHRISTOPHER P. MOZAK
- 主分类号: G06F11/07
- IPC分类号: G06F11/07
摘要:
A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system.
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