发明申请
US20140195817A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS
审中-公开
三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
- 专利标题： THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS
- 专利标题（中）： 三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
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申请号： US13996527申请日： 2011-12-23
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公开(公告)号： US20140195817A1公开(公告)日： 2014-07-10
- 发明人: Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
- 申请人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 国际申请： PCT/US2011/067230 WO 20111223
- 主分类号： G06F21/60
- IPC分类号： G06F21/60 ; G06F9/30
摘要：
A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.