发明申请
US20140197470A1 METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
有权
形成止蚀层的方法，具有该阻挡层的半导体器件以及用于制造半导体器件的方法
- 专利标题： METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
- 专利标题（中）： 形成止蚀层的方法，具有该阻挡层的半导体器件以及用于制造半导体器件的方法
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申请号： US14218091申请日： 2014-03-18
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公开(公告)号： US20140197470A1公开(公告)日： 2014-07-17
- 发明人: Jaegoo Lee , Youngwoo Park
- 申请人： Jaegoo Lee , Youngwoo Park
- 优先权： KR10-2010-0114548 20101117
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L27/115
摘要：
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.
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