Invention Application
- Patent Title: FAST, LOW POWER COMPARATOR WITH DYNAMIC BIAS BACKGROUND
- Patent Title (中): 具有动态偏置的快速，低功率比较技术背景
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Application No.: US13773427Application Date: 2013-02-21
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Publication No.: US20140232457A1Publication Date: 2014-08-21
- Inventor: Vijayakumar Dhanasekaran
- Applicant: QUALCOMM INCORPORATED
- Main IPC: H03F3/45
- IPC: H03F3/45
Abstract:
A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.
Public/Granted literature
- US08947125B2 Fast, low power comparator with dynamic bias background Public/Granted day:2015-02-03
Information query
