Invention Application
- Patent Title: Novel Patterning Approach for Improved Via Landing Profile
- Patent Title (中): 改进通道着陆轮廓的新型图案化方法
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Application No.: US13794999Application Date: 2013-03-12
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Publication No.: US20140264902A1Publication Date: 2014-09-18
- Inventor: Chih-Yuan Ting , Chung-Wen Wu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768

Abstract:
The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.
Public/Granted literature
- US09312222B2 Patterning approach for improved via landing profile Public/Granted day:2016-04-12
Information query
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