发明申请
- 专利标题: 3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERFACES WITH HIGH BONDING ENERGY
- 专利标题(中): 具有高粘结能的低温接合界面的3D集成结构
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申请号: US14334370申请日: 2014-07-17
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公开(公告)号: US20140327113A1公开(公告)日: 2014-11-06
- 发明人: Gweltaz Gaudin
- 申请人: Soitec
- 优先权: FR1056696 20100820
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L23/00
摘要:
The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.
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