Invention Application
US20140372648A1 MULTI MASTER ARBITRATION SCHEME IN A SYSTEM ON CHIP 有权
在芯片系统中的多主要仲裁方案

MULTI MASTER ARBITRATION SCHEME IN A SYSTEM ON CHIP
Abstract:
A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.
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