发明申请
US20150004723A1 Method of Inspecting Misalignment of Polysilicon Gate 有权
检查多晶硅门偏移的方法

Method of Inspecting Misalignment of Polysilicon Gate
摘要:
A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.
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