发明申请
US20150091923A1 PROCESSOR ARCHITECTURE USING A RISC PROCESSOR AND MULTIPLE ADJUNCT PROCESSORS
有权
使用RISC处理器和多个ADJUNCT处理器的处理器架构
- 专利标题： PROCESSOR ARCHITECTURE USING A RISC PROCESSOR AND MULTIPLE ADJUNCT PROCESSORS
- 专利标题（中）： 使用RISC处理器和多个ADJUNCT处理器的处理器架构
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申请号： US14547947申请日： 2014-11-19
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公开(公告)号： US20150091923A1公开(公告)日： 2015-04-02
- 发明人: James Albert Luckett, JR. , Chad Michael Rowlee , Shengli Fu
- 申请人： MYTH INNOVATIONS, INC.
- 主分类号： G06F15/82
- IPC分类号： G06F15/82 ; G06T1/20
摘要：
A method for processing data comprising activating a reduced instruction set processor. Activating a basic input output system of the reduced instruction set processor. Activating a multiple boot loader of the reduced instruction set processor after the basic input output system has been activated. Activating a hardware abstraction layer of the reduced instruction set processor after the multiple boot loader has been activated. Activating a plurality of processors coupled to the reduced instruction set processor. Activating a common language infrastructure of the reduced instruction set processor. Synchronizing a dynamic link library of each of the plurality of processors with a common language infrastructure of the reduced instruction set processor.
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