发明申请
- 专利标题: GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES
- 专利标题(中): 纳米晶体结构的III-N族晶体管
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申请号: US14581722申请日: 2014-12-23
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公开(公告)号: US20150108496A1公开(公告)日: 2015-04-23
- 发明人: Han Wui THEN , Sansaptak DASGUPTA , Marko RADOSAVLJEVIC , Benjamin CHU-KUNG , Sanaz GARDNER , Seung Hoon SUNG , Robert S. Chau
- 申请人: Intel Corporation
- 主分类号: H01L27/12
- IPC分类号: H01L27/12 ; H01L29/201 ; H01L29/06 ; H01L21/285 ; H01L29/66 ; H01L21/84 ; H01L21/02 ; H01L29/20 ; H01L29/778
摘要:
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
公开/授权文献
- US09219079B2 Group III-N transistor on nanoscale template structures 公开/授权日:2015-12-22
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