Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.